Driving apparatus of display device and driving method thereof

ABSTRACT

Disclosed is a driving apparatus of a display device having a plurality of pixels. The driving apparatus includes a signal generator that generates a shutdown signal, first and second register units that store register values, a gate driver that transmits gate signals to the pixels, a data driver that transmits data voltages to the pixels, and a signal controller that controls the gate driver and the data driver based on the register values of the first and second register units. An initialization of the register values stored in the register units is controlled based on the shutdown signal. The first register unit and the second register unit have the same construction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2007-0013141 filed in the Korean IntellectualProperty Office on Feb. 8, 2007, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a driving apparatus of a display deviceand a driving method thereof.

(b) Description of the Related Art

In general, liquid crystal displays (LCDs) include two display panelsrespectively having pixel electrodes and a common electrode, and aliquid crystal layer having dielectric anisotropy interposedtherebetween. The pixel electrodes are arranged in a matrix andconnected to switching devices such as thin film transistors (TFTs) soas to be sequentially supplied with data voltages in units of a pixelrow. The common electrode is disposed over the entire surface of onedisplay panel and is supplied with a common voltage. Alternatively, thecommon electrode may be formed on the same panel as that having thepixel electrodes. In terms of a circuit, a pixel electrode, the commonelectrode, and the liquid crystal layer interposed therebetweenconstitute a liquid crystal capacitor. The liquid crystal capacitortogether with the switching element connected thereto becomes a unit ofa pixel.

The LCD generates electric fields by applying voltages to the pixelelectrodes and the common electrode, and the strength of the electricfields applied thereto are varied in order to adjust transmittance oflight passing through the liquid crystal layer, thereby displayingimages.

The LCD also includes switching elements each of which is connected to apixel electrode, gate lines and data lines connected to the switchingelements, a gate driver that transmits gate signals to the gate lines, adata driver that transmit data voltages to the data lines, and a controlsignal that controls the gate driver and the data driver.

The LCD selectively uses a plug and play (P&P) mode or a serialperipheral interface (SPI) mod e to define values of registers requiredfor operating each element such as the gate driver, the data driver, andthe signal controller.

When the SPI mode is used in the LCD, the values of the registers aredefined based on data applied from an external device in synchronizationwith a clock signal such that the LCD operates.

When the P&P mode is used in the LCD, the values of the registers areinitialized with predetermined initial values by a shutdown functionsignal SD in the application of the power supply, such that the LCDoperates.

However, when the values of the registers are changed by, for example,electrical shock or electrostatic discharge applied from the outside,the LCD does not operate properly.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a driving apparatusis provided, the driving apparatus including a signal generator thatgenerates a shutdown signal, a plurality of register units that storeregister values, a register value adjustor that compares the registervalues, and when at least one register value of the register valuesstored in the same address has a different value, controls a state ofthe shutdown signal, wherein an initialization of the register valuesstored in the register units is controlled based on the shutdown signal.

The signal generator may be a plug and play unit.

The register units may include a first register unit and a secondregister unit, and the first register unit and the second register unithave the same construction.

The register value adjustor may compare the register values stored inthe same address in at least one part of the first and second registerunits, and when the compared register values are different, it maycontrol the state of the shutdown signal to initialize the registervalues of the first and second register units.

The first and second register units may store values of a fixed registerand a variable register, and the values of the fixed register are notchanged, but the values of the variable register are changed.

The register units may include a first register unit that stores thevalues of a fixed register and a variable register, and a secondregister unit that stores the values of the variable register.

The register value adjustor may compare the values of the variableregister of the first register unit and the values of the variableregister of the second register unit.

According to another embodiment of the present invention, a drivingapparatus of a display device having a plurality of pixels is provided,the driving apparatus including a signal generator that generates ashutdown signal, a plurality of register units that store registervalues, a gate driver that transmits gate signals to the pixels, a datadriver that transmits data voltages to the pixels, and a signalcontroller that controls the gate driver and the data driver based onthe register values of the register units, wherein an initialization ofthe register values stored in the register units is controlled based onthe shutdown signal.

The register units may include a first register unit and a secondregister unit, and the first register unit and the second register unithave the same construction.

The first and second register units may store values of a fixed registerand a variable register, and the values of the fixed register may be notchanged, but the values of the variable register may be changed.

The register units may include a first register unit that stores thevalues of a fixed register and a variable register, and a secondregister unit that stores the values of the variable register.

The register value adjustor may compare the register values stored inthe same address in at least one part of the first and second registerunits, and when the compared register values are different, it maycontrol the state of the shutdown signal to initialize the registervalues of the first and second register units.

According to further another embodiment of the present invention, adriving method of a display device having a plug and play unit thatgenerates a shutdown signal, and a plurality of register units isprovided, the driving method including reading register values stored inat least one part of the register units, comparing the read registervalues stored in the same address, and changing a state of the shutdownsignal when an address having different register values from each otherexists, to initialize the register values of the register units withinitial values.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the present invention is described below indetail with reference to the accompanying drawings wherein:

FIG. 1 is a block diagram of an LCD according to an exemplary embodimentof the present invention;

FIG. 2 is an equivalent circuit diagram of a pixel of an LCD accordingto an exemplary embodiment of the present invention;

FIG. 3 is a block diagram of the signal controller shown in FIG. 1;

FIG. 4 is an operation flow chart of the plug and play unit shown inFIG. 1;

FIG. 5 is an operation flow chart of the register value adjuster shownin FIG. 3; and

FIG. 6 is an example of the register units according to an exemplaryembodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention is described below more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown. As those skilled in the art realize, the describedembodiments may be modified in various different ways, all withoutdeparting from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, and regions areexaggerated for clarity. Like reference numerals designate like elementsthroughout the specification. It will be understood that when an elementsuch as a layer, film, region, or substrate is referred to as being “on”another element, it can be directly on the other element or interveningelements may also be present. In contrast, when an element is referredto as being “directly on” another element, there are no interveningelements present.

Referring to FIGS. 1, 2, and 6, an LCD according to an exemplaryembodiment of the present invention is described.

FIG. 1 is a block diagram of an LCD according to an exemplary embodimentof the present invention, and FIG. 2 is an equivalent circuit diagram ofa pixel of an LCD according to an exemplary embodiment of the presentinvention. FIG. 6 is an example of the register units according to anexemplary embodiment of the present invention.

Referring to FIG. 1, an LCD according to an embodiment includes a liquidcrystal (LC) panel assembly 300, an input unit 610, a P&P (plug andplay) unit 620, a gate driver 400 and a data driver 500 that are coupledwith the panel assembly 300, a gray voltage generator 800 coupled withthe data driver 500, and a signal controller 600 controlling the aboveelements.

The panel assembly 300 includes a plurality of signal lines G₁-G_(n) andD₁-D_(m) and a plurality of pixels PX connected to the signal linesG₁-G_(n) and D₁-D_(m) and arranged substantially in a matrix. In thestructural view shown in FIG. 2, the panel assembly 300 includes lowerand upper panels 100 and 200 facing each other, and an LC layer 3interposed between the panels 100 and 200.

The signal lines include a plurality of gate lines G₁-G_(n) transmittinggate signals (also referred to as “scanning signals” hereinafter) and aplurality of data lines D₁-D_(m) transmitting data voltages. The gatelines G₁-G_(n) extend substantially in a row direction and substantiallyparallel to each other, while the data lines D₁-D_(m) extendsubstantially in a column direction and substantially parallel to eachother.

Referring to FIG. 2, each pixel PX, for example a pixel PX connected tothe i-th gate line G_(i) (i=1, 2, . . . , n) and the j-th data lineD_(j) (j=1, 2, . . . , m), includes a switching element Q connected tothe signal lines G_(i) and D_(j), and an LC capacitor Clc and a storagecapacitor Cst that are connected to the switching element Q. The storagecapacitor Cst may be omitted.

The switching element Q is disposed on the lower panel 100 and has threeterminals, i.e., a control terminal connected to the gate line G_(i), aninput terminal connected to the data line D_(j), and an output terminalconnected to the LC capacitor Clc and the storage capacitor Cst.

The LC capacitor Clc includes a pixel electrode 191 disposed on thelower panel 100 and a common electrode 270 disposed on the upper panel200 as two terminals. The LC layer 3 disposed between the two electrodes191 and 270 functions as a dielectric of the LC capacitor Clc. The pixelelectrode 191 is connected to the switching element Q, and the commonelectrode 270 is supplied with a common voltage Vcom and covers anentire surface of the upper panel 200. Unlike in FIG. 2, the commonelectrode 270 may be provided on the lower panel 100, and at least oneof the electrodes 191 and 270 may have a shape of a bar or a stripe.

The storage capacitor Cst is an auxiliary capacitor for the LC capacitorClc. The storage capacitor Cst includes the pixel electrode 191 and aseparate signal line, which is provided on the lower panel 100, overlapsthe pixel electrode 191 via an insulator, and is supplied with apredetermined voltage such as the common voltage Vcom. Alternatively,the storage capacitor Cst includes the pixel electrode 191 and anadjacent gate line called a previous gate line, which overlaps the pixelelectrode 191 via an insulator.

For color display, each pixel uniquely represents one of primary colors(i.e., spatial division) or each pixel sequentially represents theprimary colors in turn (i.e., temporal division) such that a spatial ortemporal sum of the primary colors is recognized as a desired color. Anexample of a set of primary colors includes red, green, and blue. FIG. 2shows an example of the spatial division in which each pixel includes acolor filter 230 representing one of the primary colors in an area ofthe upper panel 200 facing the pixel electrode 191. Alternatively, thecolor filter 230 is provided on or under the pixel electrode 191 on thelower panel 100.

One or more polarizers (not shown) are attached to the panel assembly300.

Referring to FIG. 1 again, the input unit 610 inputs desired data andother information to the LCD, and may be a keyboard, a mouse, or acontrol panel.

The P&P unit 620 is connected to the input unit 610, and is suppliedwith power supply for operating the LCD from a power source (not shown).The P&P unit 620 generates a shutdown signal SD of which level ischanged to transmit to the signal controller 600. Accordingly, the P&Punit 620 may be a signal generator.

The gray voltage generator 800 generates a full number of gray voltagesor a limited number of gray voltages (referred to as “reference grayvoltages” hereinafter) related to the transmittance of the pixels PX.Some of the (reference) gray voltages have a positive polarity relativeto the common voltage Vcom, while the other of the (reference) grayvoltages have a negative polarity relative to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G₁-G_(n) of the panelassembly 300, and synthesizes a gate-on voltage Von and a gate-offvoltage Voff to generate the gate signals for application to the gatelines G₁-G_(n).

The data driver 500 is connected to the data lines D₁-D_(m) of the panelassembly 300 and applies data voltages, which are selected from the grayvoltages supplied from the gray voltage generator 800, to the data linesD₁-D_(m). However, when the gray voltage generator 800 generates a fewof the reference gray voltages rather than all the gray voltages, thedata driver 500 may divide the reference gray voltages to generate thedata voltages from among the reference gray voltages.

As shown in FIG. 3, the signal controller 600 includes first and secondregister units 601 and 602, and a register value adjuster 603. Theregister value adjuster 603 is connected to the first and secondregister units 601 and 602, and the P&P unit 620. The signal controller600 controls the gate driver 400 and the data driver 500 based onregister values of each register unit 601 and 602.

The first and second register units 601 and 602 store values forcontrolling the image displaying, the power supplying, and the grayvoltage controlling. The construction of the first and second registerunits 601 and 602 is the same. An example of the register units 601 and602 is illustrated in FIG. 6.

In FIG. 6, values stored in addresses “00h” and “0Fh” are values ofregisters involving the image displaying, values stored in addressesfrom “10h” to “1Bh” are values of registers involving the generating ofa plurality of voltages, and values stored in addresses from “30h” to“39h” are values of registers involving the gray voltage generating.

The register units 601 and 602 include a plurality of resisters,respectively. The registers are divided into fixed registers connectedto predetermined voltages, for example a ground voltage or about +5Vthrough wires, and thereby having fixed values, first variable registersof which values are varied by a user, and second variable registers ofwhich values are logically varied by signals from an external device.

In the embodiment the register units 601 and 602 are the same, and theystore values of the fixed registers and the first and second variableregisters. However, alternatively, one of the register units 601 and 602may store values of the first and second variable registers.

In this embodiment, the register units 601 and 602 are included in thesignal controller 600. Alternatively, the register units 601 and 602 arestored in a memory unit separate from the signal controller 600.

The register value adjuster 603 compares register values of the firstand second register units 601 and 602, respectively. When at least oneregister having a different value exists, the register value adjuster603 controls the P&P unit 620, to control a state of the showdown signalCD.

Each of driving devices 400, 500, 600, and 800 may include at least oneintegrated circuit (IC) chip mounted on the LC panel assembly 300 or ona flexible printed circuit (FPC) film in a tape carrier package (TCP)type, which are attached to the panel assembly 300. Alternatively, atleast one of the driving devices 400, 500, 600, and 800 may beintegrated into the panel assembly 300 along with the signal linesG₁-G_(n) and D₁-D_(m) and the switching elements Q. As a furtheralternative, all the driving devices 400, 500, 600, and 800 may beintegrated into a single IC chip, but at least one of the drivingdevices 400, 500, 600, and 800 or at least one circuit element in atleast one of the driving devices 400, 500, 600, and 800 may be disposedout of the single IC chip.

Below the operation of the above-described LCD is described in detail.

For operating the LCD, when a power supply is supplied from a powersource, the P&P unit 620 outputs the shutdown signal SD, of which astate has a high level voltage H for a predetermined time, and then ischanged to a low level voltage L.

When the state of the shutdown signal SD is changed from the high levelvoltage H to the low level voltage L, the signal controller 600initializes register values of the first and second register units 601and 602 with predetermined initial values. However, when the signalinputting through the input unit 610 does not occur for a predeterminedtime, the P&P unit 620 changes the state of the shutdown signal SD fromthe high level voltage H. Thus, the P&P unit 620 shunts down theoperation of the LCD, that is, the operation of the LCD is converted toa shutdown operation mode.

The operations of the P&P unit 620 is described below in detail withreference to FIG. 4.

When a power supply for operating the LCD is applied from an externaldevice, and thereby the P&P unit 620 starts to operate (step S10), theP&P unit 620 changes a state of the shutdown signal SD from a high levelvoltage H to a low level voltage L, to transmit it to the signalcontroller 600. When the state of the shutdown signal SD is changed fromthe high level voltage H to the low level voltage L, the signalcontroller 600 initializes register values of the first and secondregister units 601 and 602 with predetermined initial values, andcontrols the gate driver 400 and data driver 500 to display images basedon input image signals R, G, and B.

Next, the P&P unit 620 reads signals from the input unit 610, anddetermines whether the input unit 610 is operated (steps S12 and S13).

When the input unit 610 is not operated, the P&P unit 620 determineswhether non-operation time of the input unit 610 exceeds a predeterminedtime (step S14).

When the non-operation time does not exceed the predetermined time, theP&P unit 620 determines whether the input section 610 is operated (stepS13).

However, when the non-operation time exceeds the predetermined time, theP&P unit 620 outputs the shutdown signal SD having the high levelvoltage H to transmit it to signal controller 600 (step 15).

Thereby, the signal controller 600 controls a voltage generator (notshown) such that the signal controller 600 changes an operation mode ofthe LCD to the shutdown operation mode in which the minimum operationsof the LCD are performed. Therefore, undesired power consumption of theLCD is decreased.

However, in step (S13), when the input unit 610 operates such thatsignals are input from the input unit 610, the P&P unit 620 determineswhether the state of the shutdown signal SD is the high level voltage H,that is, the operation mode of the LCD is the shutdown operation mode(step S16).

When the state of the shutdown signal SD maintains not the high levelvoltage H but the low level voltage L, the P&P unit 620 goes to the step(S12) to determine the operation state of the input unit 610.

However, when the state of the shutdown signal SD maintains the highlevel voltage H, the P&P unit 620 changes the state of the shutdownsignal SD to the low level voltage L (step 17), to convert the operationmode of the LCD from the shutdown operation mode to a normal operationmode.

Thereby, the signal controller 600 initializes register values of thefirst and second register units 601 and 602 with the initial value, andthus controls the LCD to normally display images.

When the register values of the first and second register units 601 and602 are defined by the initial values in accordance with the shutdownsignal SD by operating the P&P unit 620, the signal controller 600 issupplied with input image signals R, G, and B and input control signalsfor controlling the display thereof from an external graphics controller(not shown). The input image signals R, G, and B contain luminanceinformation of pixels PX, and the luminance has a predetermined numberof grays, for example 1024 (=2¹⁰), 256 (=2⁸), or 64 (=2⁶) grays. Theinput control signals include a vertical synchronization signal Vsync, ahorizontal synchronization signal Hsync, a main clock signal MCLK, and adata enable signal DE.

On the basis of the input control signals and the input image signals R,G, and B, the signal controller 600 generates gate control signals CONT1and data control signals CONT2 and it processes the image signals R, G,and B to be suitable for the operation of the panel assembly 300 and thedata driver 500. The signal controller 600 sends the gate controlsignals CONT1 to the gate driver 400 and sends the processed imagesignals DAT and the data control signals CONT2 to the data driver 500.

When at least one register value of the first and second register units601 and 602 is changed due to, for example, an electrostatic dischargeor electrical shock applied from the outside, the register valueadjuster 603 of the signal controller 600 initializes the registervalues of the first and second register units 601 and 602, to normallychange the resister values to initial values. An operation of theregister value adjuster 603 will be described in detail later.

The gate control signals CONT1 include a scanning start signal STV forinstructing to start scanning and at least one clock signal forcontrolling the output period of the gate-on voltage Von. The gatecontrol signals CONT1 may include an output enable signal OE fordefining the duration of the gate-on voltage Von.

The data control signals CONT2 include a horizontal synchronizationstart signal STH for informing of start of data transmission for a rowof pixels PX, a load signal LOAD for instructing to apply the datavoltages to the data lines D₁-D_(m), and a data clock signal HCLK. Thedata control signal CONT2 may further include an inversion signal RVSfor reversing the polarity of the data voltages (relative to the commonvoltage Vcom).

Responsive to the data control signals CONT2 from the signal controller600, the data driver 500 receives a packet of the digital image signalsDAT for the row of pixels PX from the signal controller 600, convertsthe digital image signals DAT into analog data voltages selected fromthe gray voltages, and applies the analog data voltages to the datalines D₁-D_(m).

The gate driver 400 applies the gate-on voltage Von to a gate lineG₁-G_(n) in response to the gate control signals CONT1 from the signalcontroller 600, thereby turning on the switching transistors Q connectedthereto. The data voltages applied to the data lines D₁-D_(m) are thensupplied to the pixels PX through the activated switching transistors Q.

A difference between a data voltage and the common voltage Vcom appliedto a pixel PX is represented as a voltage across the LC capacitor Clc ofthe pixel PX, which is referred to as a pixel voltage. The LC moleculesin the LC capacitor Clc have orientations depending on the magnitude ofthe pixel voltage, and the molecular orientations determine thepolarization of light passing through the LC layer 3. The polarizer(s)converts light polarization to light transmittance such that the pixelPX has a luminance represented by a gray of the data voltage.

By repeating this procedure by a unit of a horizontal period (which isalso referred to as “1H” and is equal to one period of the horizontalsynchronization signal Hsync and the data enable signal DE), all gatelines G₁-G_(n) are sequentially supplied with the gate-on voltage Von,thereby applying the data voltages to all pixels PX to display an imagefor a frame.

When the next frame starts after one frame finishes, the inversionsignal RVS applied to the data driver 500 is controlled such that thepolarity of the data voltages is reversed (which is referred to as“frame inversion”). The inversion signal RVS may also be controlled suchthat the polarity of the data voltages flowing in a data line areperiodically reversed during one frame (for example, row inversion anddot inversion), or the polarity of the data voltages in one packet arereversed (for example, column inversion and dot inversion).

Referring to FIG. 5 as well as FIG. 3, the operation of the registervalue adjuster 603 of the signal controller 600 is described below indetail.

FIG. 5 is an operation flow chart of the register value adjuster 603.

When the operation of the register value adjuster 603 starts (step S20),the register value adjuster 603 reads register values of the first andsecond register units 601 and 602 (step S21).

At this time, the register value adjuster 603 reads values of first andsecond variable registers, of which values are arbitrary changed by auser, instead of reading all register values of the first and secondregister units 601 and 602. Thus, after the register value adjuster 603reads the values of the first and second variable registers that arestored in corresponding addresses, the register value adjuster 603compares the values of the first and second variable resisters stored inthe same address, respectively (step S22).

Alternatively, when the constructions of the first and second registerunits 601 and 602 are different from each other, and thereby one of thefirst and second register units 601 and 602 includes fixed registers,and the first and second variable registers, and the other of themincludes the first and second variable registers, the register valueadjuster 603 compares values of the first and second variable registersof the first and second register units 601 and 602.

At this time, when at least one register of the first and secondvariable registers stored in the same address has a different value(step S23), the register value adjuster 603 activates an initial signalINI, for example, from a low level voltage L to a high level voltage H,to transmit it to the P&P unit 620 (step 24).

Thereby, the P&P unit 620 outputs the shutdown signal SD having a highlevel voltage H for a predetermined time and then changing to a lowlevel voltage L in response to the activated initial signal INI, totransmit it to the first and second register units 601 and 602.

When the state of the shutdown signal SD is changed from the high levelvoltage H to the low level voltage L, the first and second registerunits 601 and 602 initialize the register values thereof withpredetermined initial values.

Thereby, when the values of the first and second variable registers arechanged due to the electro static discharge or the electrical shock, theregister values of the first and second register units 601 and 602 arerecovered to the initial values by the shutdown signal SD.

However, when all registers of the first and second variable registersstored in the same address have the same values (step S23),respectively, the register value adjuster 603 goes to step (S21), tocompare the register values of the first and second register units 601and 602.

As described above, since instead of the comparison of all registervalues of the first and second register units 601 and 602, the values ofthe first and second variable registers are compared to each other,processing time of the register value adjuster 603 decreases and theconstruction thereof is simplified.

In this embodiment, for determining change of the register values of aregister unit due to the electrostatic discharge or the electricalshock, one separate register is added, but two or more separateregisters may be added to improve reliability of the operation of theregister value adjuster 603.

According to the embodiment, when register values of a register unit arechanged due to electrostatic discharge and electrical shock a state of ashutdown signal output from the P&P unit is controlled without regard tothe operation of the P&P unit, and thereby a state of the register unitis initialized. Thus, the changed register values are normally recoveredto initial values, to normally display images in an LCD.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A driving apparatus comprising: a signal generator adapted togenerate a shutdown signal; a plurality of register units adapted tostore register values; a register value adjuster operative to compareregister values at an address in each of the plurality of registerunits, and when at least one register value stored in the same addressin each of the plurality of register units is different, the registervalue adjuster controls a state of the shutdown signal, wherein aninitialization of the register values stored in the register units iscontrolled based on the shutdown signal.
 2. The driving apparatus ofclaim 1, wherein the signal generator is a plug and play unit.
 3. Thedriving apparatus of claim 1, wherein the register units comprise afirst register unit and a second register unit.
 4. The driving apparatusof claim 3, wherein the circuitry of first register unit and thecircuitry of second register unit are the same.
 5. The driving apparatusof claim 3, wherein the register value adjuster compares the registervalues stored in the same address in at least one part of the first andsecond register units, and when at least one of the compared registervalues is different, controls a state of the shutdown signal toinitialize the register values of the first and second register units.6. The driving apparatus of claim 5, wherein the first and secondregister units store values of a fixed register and a variable register,and the values of the fixed register are not changed but the values ofthe variable register are changed.
 7. The driving apparatus of claim 6,wherein the register value adjuster compares the values of the variableregister of the first register unit and the values of the variableregister of the second register unit.
 8. The driving apparatus of claim1, wherein the register units comprise: a first register unit thatstores register values of a fixed register and register values of avariable register, and a second register unit that stores registervalues of the variable register.
 9. The driving apparatus of claim 8,wherein the register value adjuster compares the register values of thevariable register of the first register unit and the register values ofthe variable register of the second register unit.
 10. A drivingapparatus for a display device having a plurality of pixels, the drivingapparatus comprising: a signal generator adapted to generate a shutdownsignal; a plurality of register units adapted to store register values;a gate driver that transmits gate signals to the pixels; a data driverthat transmits data voltages to the pixels; and a signal controller thatcontrols the gate driver and the data driver based on the registervalues of the register units, wherein an initialization of the registervalues stored in the register units is controlled based on the shutdownsignal.
 11. The driving apparatus of claim 10, wherein the registerunits comprise a first register unit and a second register unit.
 12. Thedriving apparatus of claim 11, wherein the first and second registerunits store values of a fixed register and a variable register, and thevalues of the fixed register are not changed but the values of thevariable register are changed.
 13. The driving apparatus of claim 10,wherein the register units comprise: a first register unit that storesregister values of a fixed register and register values of a variableregister, and a second register unit that stores register values of thevariable register.
 14. The driving apparatus of claim 10, wherein theregister value adjuster compares the register values stored in the sameaddress in at least one part of the first and second register units, andwhen the compared register values are different, controls a state of theshutdown signal to initialize the register values of the first andsecond register units.
 15. A driving method of a display device having aplug and play unit that generates a shutdown signal, and a plurality ofregister units, the driving method comprising: reading register valuesstored in at least one part of the register units; comparing the readregister values stored in the same address; and changing a state of theshutdown signal when an address having a different register value fromeach other exists, to initialize the register values of the registerunits with initial values.